A HIGH SPEED POWER-DOWN DECODER CIRCUIT
Original Publication Date: 1982-Jan-01
Included in the Prior Art Database: 2001-Oct-10
The requirement of low power standby mode operation for today's static type MOS memories, such as ROM, EPROM and EEPROM, has degraded speed of these products due to a slower access time for chip enable than for an address, The slower chip enable access time is caused mainly by shortcomings of the existing power down decoder circuits that reset all word lines high and bit lines low during the power-down period. Discharging of all word lines, except the one selected, during power up creates a negative voltage on the bit lines through capacitive coupling. This can cause unselected column gating transistors to turn on which retards the transition of the selected bit line from low to high, resulting in longer chip enable access time.