IMPROVED SAMPLE AND HOLD CONTROL CIRCUITRY
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2001-Oct-08
Analog to digital converter systems operating on rapidly changing input waveforms require very small control signal jitter in the sampler to not degrade measurement performance. In addition, for systems employing a sample and hold, fast acquisition and low pedestal error nonlinearity are desirable. It is difficult to simultaneously achieve this with conventional FET switching. The circuit presented here offers improved performance by using a bipolar Gilbert cell to charge the holding capacitor. This configuration can be switched rapidly for low aperture jitter, with inherently zero dif- ferential pedestal error. The large charging currents which allow fast acquisition can be turned off dur- ing hold mode for low power dissipation.