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A HIGH SPEED, LOW NOISE, SYNCHRONIZER CIRCUIT WITH A SQUARE WAVE OUTPUT

IP.com Disclosure Number: IPCOM000005490D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2001-Oct-09
Document File: 3 page(s) / 104K

Publishing Venue

Motorola

Related People

Authors:
Kenneth A. Hansen

Abstract

Logic designs are typically done asynchronously because the design is simplified, the number of gates is minimized, and the current drain is minimized. However, in an a synchronous design it is often required to synchronize with respect to some reference time base. Various approaches have been used in the past to perform the synchronization. The simplest approach uses a D type flip-flop as asyn- chronizer. All of these approaches have at least one of the following shortcomings: (1) slow speed, (2) 'i high noise, or (3) non-square wave output.