SHIFT REGISTER FIFO

Publishing Venue

Motorola

Related People

Abstract

This FIFO (First In, First Out Register) is implemented as a Shift Register with a selector on the out- put of each cell location such that the stored data in the cell(s) may be either shifted to the next sequen- tial cell(s) or gated to the output of the FIFO. The FIFO may be from 1 ton bits in length and one tom bits In width.

!@l: MOTOROLA Technical Developments Volume 3 March 1983

SHIFT REGISTER FIFO

By Robert Pancost For Yoseph Linde

   This FIFO (First In, First Out Register) is implemented as a Shift Register with a selector on the out- put of each cell location such that the stored data in the cell(s) may be either shifted to the next sequen- tial cell(s) or gated to the output of the FIFO. The FIFO may be from 1 ton bits in length and one tom bits In width.

   The location of the data to be output (READ) from the FIFO is tracked by a single UP/DOWN counter, the decoded outputs of this counter providing the select lines to output of each cell. This counter is reset (equal zero) upon initialization of the FIFO.

   As data is input (WRITE) to the FIFO, the data in each cell location is shifted to the next sequential cell location while the input data is stored in the first cell location. The counter is incremented during the write, indicating the location of the next data to read. If all cell locations are full (counter decode max) and a write signal is received, OVERFLOW status will be output by the FIFO.

   As data is output (READ) from the FIFO, the counter is decremented indicating that the data has been used thus pointing to the next data to output. If all cell locations are empty (counter equal zero) and a read signal is received, UNDERFLOW status will be output from the FIFO.

This implementation of a FIFO has simpler control logic and reduces from two to one the number of counters requi...