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Methods of Scan Pattern Manipulation

IP.com Disclosure Number: IPCOM000005542D
Original Publication Date: 2001-Oct-12
Included in the Prior Art Database: 2001-Oct-12

Publishing Venue


Related People

John C. Potter Alfred L. Crouch


In the world of System-on-a-Chip (SoC) integration, one of the more significant cost drivers is the test integration. The volume of logic and memory, coupled with the volume of vectors and separate vector sets, requires test scheduling to meet power, package, test bandwidth, and tester limitations. Test scheduling has two main components, a test architecture that allows or enables test selectable portions of the chip, and techniques for combining test groupings into schedulable sections. This publication discusses several methods of scan pattern and BIST pattern manipulation for scheduling, the test architecture requirements, and the information needed to perform the test pattern manipulation.