ITERATIVE CMOS MAGNITUDE COMPARATOR CELL
Original Publication Date: 1985-Oct-01
Included in the Prior Art Database: 2001-Oct-16
An iterative cell for digital magnitude comparision is described. This cell uses the fast-carry propagation chain principle. The generation, propagation, and inhibition of generation of the cell logic signals are described. Finally, a CMOS realization is illustrated as one possible implementation of this cell.