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IMPROVED FREQUENCY SYNTHESIZER

IP.com Disclosure Number: IPCOM000005589D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-17

Publishing Venue

Motorola

Related People

Authors:
William J. Ooms

Abstract

A phase locked loop (PLL) frequency synthesizer is normally constructed using a stable crystal oscillator divided to a low reference fequency, and then using a phase locked loop with a programmable divider in the feedback loop to effectively multiply the reference frequency to some output frequency. One constraint of this method is that the output frequency is an integral multiple of the reference frequency.