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SEPARATION OF EXCEPTION RECOGNITION, PRIORITIZATION, AND STATE MAINTENANCE

IP.com Disclosure Number: IPCOM000005599D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-18
Document File: 1 page(s) / 81K

Publishing Venue

Motorola

Related People

Authors:
Bill Moyer Doug MacGregor Bob Thompson

Abstract

As processors become increasingly complex, so do the exception recognition and handling requirements of the processor. Complex processors, such as the MC68000, MC68010, and MC68020 were designed to recognize and handle a number of internally and externally generated exception conditions. Among these are interrupts, bus errors, addressing errors, illegal instruction, privilege violations, division by zero, trace exceptions, emula- tion exceptions, and other various exceptions which might occur in a processing system.