MACROCELL ARRAY HAVING MIXED SINGLE AND DOUBLE DRIVE
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-18
Existing CMOS gate arrays having a plurality of semiconductor devices within a plurality of cells use a single drive level for the cells resulting in the drive level being either too high or too low for many situations. A typical cell consists of two P-channel and two N-channel transistors, resulting in asingle two-input logic gate.