Browse Prior Art Database

MEMORY MANAGEMENT FOR TOKEN-BUS LAN

IP.com Disclosure Number: IPCOM000005601D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-18

Publishing Venue

Motorola

Related People

Authors:
Orly Kremien Yehuda Shvager

Abstract

To support the IEEE 802.4 message priorities, the Token Bus Controller(TBC) chip uses a powerful, flexi- ble memory and buffer management structure and maintains four transmit queues and four receive queues. The RAM based structures that the TBC uses for buffer management include: Frame Descriptors (FD) List(s) - contain a linked list of frame descriptors. Separate lists of FD's are maintained for a free FD pool, four receive queues, and four transmit queues. A frame descriptor con- sists of frame attributes (source address, destination address, size, etc.), a pointer to the associated BD list and a pointer to the next FD in the queue.