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TIMING GENERATOR Disclosure Number: IPCOM000005608D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-18

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Hiroshi Sakamoto


The circuit of Fig. 1 is designed to generate an output signal VO whose leading and trailing edges appear after predetermined two separate period of time Tl and T2, with respect to the transient timings of an input signal Vi.