Browse Prior Art Database

MICROPROCESSOR ARCHITECTURE

IP.com Disclosure Number: IPCOM000005616D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-19
Document File: 3 page(s) / 93K

Publishing Venue

Motorola

Related People

Authors:
Kuppuswamy Raghunathan Robert J. Skruhak Herchel A. Vaughn

Abstract

The architecture of the MC68HCll family of CMOS microcomputers provides high throughput with fewer internal busses. The use of fewer internal busses reduces the number of register transfer signals and reduces the current which is required for the internal busses. The improvement is due largely to judiciously placed transfers, bi-directional transfers, a pre-charged bus which can be used on either phase of the system clock and direct accumulator transfers to the ALU.