Browse Prior Art Database

Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-19

Publishing Venue


Related People

Dave Mothersole Bill Moyer


Todays 32.bit architectures have been crafted to include a full compliment of instructions that deal with the manipulation of bit operands and fields. These instructions include some operations that are not easily implemented to yield both performance and reasonable cost. Examples of these operations include bit opera- tions such as arithmetic and logical shifting, bit rotating, bit manipulation and bitfield manipulation, and multi- ply/divide. The MC66020 32.bit processor utilizes a unique set of algorithms to facilitate optimal performance of the above operations while maintaining a reasonable implementation cost. The algorithms require the use of several key mechanisms such as a32-bit barrel shifter, a pair of source and destination registers, and acom- plex pipelined control mechanism. These algorithms together with the above hardware allow most bit opera- tions to be performed in a single operation cycle as opposed to the traditional serial shift mechanism where the performance is determined by the number of bits in the field or the number of bit positions the operation entails. These algorithms have been expanded to allow the multiply instructions to include a fast scanning of overlapping fields of bits in the multiplicand.