Browse Prior Art Database

DATA CACHE LOAD INHIBIT ATTRIBUTE STORED IN TRANSLATION TABLES

IP.com Disclosure Number: IPCOM000005622D
Original Publication Date: 1986-Oct-01
Included in the Prior Art Database: 2001-Oct-22

Publishing Venue

Motorola

Related People

Authors:
Brad Cohen

Abstract

A fundamental concern in data cache design is insuring that the data stored in the cache is "up to date." The contents of a main memory location, which is stored in the data cache, may be altered, such that the cache no longer reflects the value stored in the main memory location. The cache then contains what is termed "stale data:'This phenomenon commonly occurs in areas of inter-cpu communication (mailboxes or semaphore loca- tions) or in areas which will experience DMA activity, Stale data is a problem to be avoided in any data cache, but is more severe in logical bus data caches. Physical data caches which implement stale data invalidation schemes first detect physical memory writes, then invalidate any stored entries which correspond to the written main memory locations. Main memory resides on the physical bus, thus in addition to the detection/invalidation of a physical data cache, control circuitry for a logical data cache must obtain the (all) inverse mapping(s) associated with the physical location which is altered, to determine which logical address location(s) in the cache to invalidate.