DUAL AMPLIFIER HIGH RESOLUTION CMOS SENSING
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-22
In NMOS DRAM's almost every column sense amplifier circuit which senses and then amplifies voltage difference across pair of bit lines employs dual timing scheme. That is, referring to Figure 1, a slow pull-down on Qss which serves as signal sensing, followed by a strong pull-down on Qsf which serves as signal amplifica- tion. This is justified by the fact that, to the first order, the tolerable imbalances in transistor gain of the cross- latching pair is not only affected by the initial signal strength, but also the voltage level of the common pull- down node, vso. The higher this common node voltage, the more tolerance in imbalances of the transistor gain is allowed.