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Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-23
Document File: 4 page(s) / 157K

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Yehuda Shvager: AUTHOR [+2]


This memo describes the three TBC loopback tests, the architectural problems they solve and their coverage.

This text was extracted from a PDF file.
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Page 1 of 4

MOlVROLA Technical Developments Volume 7 October 1987


by Yehuda Shvager, Amnon Yeger, Dan Adler

This memo describes the three TBC loopback tests, the architectural problems they solve and their coverage.

Relevant TBC Architectural details:

    The TBC is a half duplex device, with independent Receive and Transmit capabilities but only one FIFO. The FIFO is configured according to the mode (TX or Rx). In TX mode, the FIFO is written into by the DMAlMAAM and read by the Serial Transmitter. In the Rx mode the FIFO is written by the Serial Receiver and read by the DMAIMAAM.

TX Mode Configuration

----w--- ---------- ----

1 DNA / f

lb I 16 - --*-- ---->I

/ FIFO 1 'IAAW 1 I

I----,-4; SyL I---> TX

I -------- I I ------------- I I---I

Rx Mode Configuration

; ,,,,A , ----I



I --------

   Since all TBC activities are Half-Duplex in nature there is never a need, in normal operation modes, for the FIFO to be read and written by the Serial side at the same time. The "problem" with this architecture is that it does not allow the design of a loopback test, wherein data is fetched from memory, transmitted, received back by shunting the Rx lines to the TX lines and written to another location in the memory.

Such a test is highly desirable for two reasons:

1. It is very simple from the user's point of view.
2. It checks the whole data path: Hardware and Firmware.

It does not make sense to change the whole chip to be full-duplex just for the sake of testing it, but some alternative testing scheme must be devised that meets the above two criteria.

TBC Test modes:

   Three test modes were designed into the TBC in order to solve the loopback problem. These tests TOGETHER provide the same degree of confidence as would a full-duplex chip architecture, while maintaining a simple user interface scheme. All three tests can be performed with INTERNAL shunt or EXTERNAL shunt (user programmable). Using INTERNAL shunting checks all the circuitry upto but not including the IO buffers, whereas the EXTERNAL shunt goes through the whole path.

0 Motorola, Inc. 1987 26

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Page 2 of 4

MOTOROLA Technical Developments Volume 7 October 1987

The tests are:


Short Full-loopback test.

Long Transmit test.

Long Receive test.



Short Fulldoopback test:

    This is aspeciallydevised test that provides somedegree of full-duplex behavior. In this test the user prepares 17 words of data in a given memory location, enables the test, and then checks to see that the 17 words were "looped-back" to different memory locations.

   This is the only test that allows the Transmitter and the Receiver to access the FIFO at the ~same time, the FIFO depth is a limiting factor for the frame length, so this test can be performed with only one frame of limited size (17 words).

   For this test special Micro-code was written so it only checks the hardware. It takes advantage of the FIFO architecture...