Browse Prior Art Database

SELF LOADING SERIAL N BIT REGISTER

IP.com Disclosure Number: IPCOM000005662D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-24

Publishing Venue

Motorola

Related People

Authors:
Barry W. Herold

Abstract

Abstract: Described herein is a unique architecture for a shift register such that the loading requires a minimal device count and the speed of operation is greatly increased over the more common architectures.