Browse Prior Art Database

CHIP CARRIER/PRINTED WIRING BOARD INTERFACE

IP.com Disclosure Number: IPCOM000005668D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-24

Publishing Venue

Motorola

Related People

Authors:
Monty W. Bai Larry Moore

Abstract

Attachment and interconnection of ceramic packages such as hermetic chip carriers to printed wiring boards (Figure 1) can result in exposure of the assemblied elements to load/stress distributions similar to those indicated in Figure 2 if the attachment/interconnections tend to closely couple the package to the PWB. Con- sequently, the reliability and durability of the package, attachments and interconnects can be severly compro- mised unless special measures are taken to minimize the levels or otherwise alleviate the effect of such loads and stresses. Use of such packages for military electronics applications often imposes particularly difficult problems in this regard due to requirements for rugged equipment capable of performing reliably during and after exposure to harsh dynamic and thermal environments.