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A FUSE PROGRAMMABLE COLUMN REDUNDANCY FOR A BYTE-WIDE SRAM

IP.com Disclosure Number: IPCOM000005673D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-25

Publishing Venue

Motorola

Related People

Authors:
Karl Wang Mark Bader Tim Egging

Abstract

State-of-the-art, high density CMOS SRAM's generally require a divided word line architecture to simul- taneously meet performance and power consumption specifications. Because of the size of these devices, a redundancy scheme is usually employed to enhance yields. However because of the extensive data bussing associated with eight outputs, column redundancy on byte-wide static RAM's with divided word lines has proven to be complicated and costly in terms of die area. The column redundancy scheme described below is unique in that it is simple to implement, causes no access time penalty, has a high ratioof redundant columns to possible defective columns, and consumes little die area.