Browse Prior Art Database

DOUBLE LAYER POLY FOR EPROM INTERCONNECT

IP.com Disclosure Number: IPCOM000005674D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-25

Publishing Venue

Motorola

Related People

Authors:
B. Morton

Abstract

Minimization of interconnect resistance is critically important in the layout of integrated circuitry in general and EPROM devices in particular. In most MOS processes there is a single layer of polysilicon which may be used as interconnect whereverthe poly resistivity is tolerable. EPROM devicesconventionally contain two poly layers, but operate in such a way as to permit only one of them to be used as interconnect, thereby imposing the same interconnect constraints as in conventional single poly processes. A new EPROM process (see ref- erence) presents the possibility of using both layers as interconnect to produce a net resistivity substantially below that of asingle layer. The resultant reduction in interconnect resistance is enough to significantly impact performance of critical circuitry.