SELF PROTECTING TRANSISTOR DESIGN
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-25
Figure 1 illustrates a self protecting transistor package 10 which includes a PTC resistor 12 interpose be- tween a semiconductor device 14 and its metal heatsinking tab 16. When the temperature of the device 14 ap- proaches its design limit, the resistance of the PTC resistor 12 increases sharply and limits the device temperature to a safe value. This approach produces very little therm0 lag between the device and the PTC resistor, and it automatically compensates for changes in the ambient temperature. The location of the PTC resistor 12, as shown, is suitable for a typical bipolar or MOS transistor as well as SCRs and triax.