PROCESS-TOLERANT HIGH LEVEL SHIFTER
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2001-Oct-26
The proposed high level shifter changes a logic signal with a voltage swing from VSS to VDD to a logic signal with a voltage swing from VSS to VCC with VCC > VDD. Its schematic is shown in FIG 1. The inputs are a logic signal Q and its inverse Qn and the outputs are the logic signals HO and its inverse HQn. This level shifter uses CMOS devices. It has the following particularities: - no static consumption - highly process-tolerant - protected against impact-ionisation.