A MIXED TECHNOLOGY GATE ARRAY WITH ECL AND BIMOS LOGIC ON A SINGLE CHIP
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2001-Oct-26
A gate array design enhances the output drive of the internal logic while maintaining zero DC powerdissipa- tion and achieves unique input/output flexibility by providing inter-facing to CMOS, TTL and ECL levels. The usable system performance is limited normally by the worst case flip-flop toggle frequency which is in the range of 150-200 MHZ depending on operating conditions.