Browse Prior Art Database

FLOATING POINT PIPELINE PARTITIONING

IP.com Disclosure Number: IPCOM000005710D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2001-Oct-30
Document File: 3 page(s) / 184K

Publishing Venue

Motorola

Related People

Authors:
Yoav Talgam Mitchell Alsup Marvin Denman Janet Sooch

Abstract

The M78000 floating point unit consists of two physical pipelines, a five stage add pipeline and asix stage multiplier pipeline, which have logically shared first and last stages. The add pipeline executes single and dou- ble precision floating point add, subtract, compare, divide instructions as well as floating point conversion to integer, integer conversion to floating point, and unsign integer divide instructions. The multiply pipeline ex- ecutes single and double precision floating point multiply and integer multiply instructions. The stages in each pipeline were balanced to assure approximately equivalent timing delays through each stage so that technology improvements will result in a uniform speed improvement throughout the pipelines. Tradeoffs of performance versus area were made where necessary to allow the floating point unit to be combined with the integer unit on a single chip.