RESULT WRITE BACK ARBITRATION SCHEME OF THE MC88100
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2001-Oct-30
The MC88100 is a highly pipelined microprocessor with multiple functional units. The pipelines of these functional units are often of varying and even variable lengths. The register file is only capable of handling one result per clock. This brings about the requirement that the write back slot must be arbitrated for in each clock to allow efficient instruction execution and pipelining.