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A Method for Modulating the Gate Coupling in Split Gate Flash Memory Devices

IP.com Disclosure Number: IPCOM000005723D
Original Publication Date: 2001-Oct-30
Included in the Prior Art Database: 2001-Oct-30

Publishing Venue


Related People

Alexander Hoefler Nina Telang


In a Split Gate Flash (SGF) electrically erasable programmable read only memory (EEPROM) technology, it is occasionally necessary to adjust the gate coupling ratio of the bitcell in order to optimize device performance or retarget device specifications after process or design changes. In this paper, we describe a method that allows a gate coupling ratio adjustment by taking advantage of the fact that the gate coupling ratio in SGF devices is determined by the thickness of the dielectric layer(s) located in the gap between floating gate and control gate. In certain implementations, there is a small silicon nitride spacer placed in this gap. The method presented in this paper proposes to change the thickness and/or dielectric properties of this small spacer deliberately, in order to modulate the thickness of the dielectric between the control gate and the floating gate, and thus the gate coupling ratio. The method can be useful for purposes such as adjustment of read currents or electric fields for program and/or erase performance, independently of other dielectric layers. The method can also improve the scalability of a bitcell in a split gate flash technology.