Browse Prior Art Database

TRENCH ISOLATION FOR MOSAIC 3

IP.com Disclosure Number: IPCOM000005728D
Original Publication Date: 1988-Oct-01
Included in the Prior Art Database: 2001-Oct-31
Document File: 2 page(s) / 175K

Publishing Venue

Motorola

Related People

Authors:
Peter Zdebel Bob Reuss

Abstract

For advanced IC's which require high performance and packing density, trench isolation is a critical ele- ment. While the device to device capacitance and lateral isolation spacing (Fig. 1, A) can be reduced with the appropriate trench refill technology, vertical metal to substrate capacitance can still be large due to thin dielec- tric films over field areas (Fig. 1, B). To reduce this interaction a dielectric film of appropriate thickness is re- quired. An integration of this process element with trench requires that either the trench surface be oxidized or thick insulators be deposited and planarized. These techniques can result in excellent isolation, however, oxidization within the trench generates considerable stress which can result in defect structures (degraded yields). Alternatively, deposition and etchback techniques are inherently time-consuming and low yielding. The planar surface shown in Fig. I is required for subsequent multi-layer metal modules, thus a thick, planarized oxide over the basic trench structure is needed.