SURFACE-GRADED LDD MOSFET
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2001-Nov-05
The purpose of this described device and process is to improve the current drive and hot-carrier effects of LDD MOSFET structures while maintaining minimum lateral source/drain overlap with the gate electrode. Athough the use of a lighter n= implant to grade the arsenic n- region for a short-channel LDD MOSFET has been shown by C. Wei et al. (IEEE Electron Device Letters, Vol. EDL.7, No. 6, June 1986, pg. 360) to provide an order of magnitude improvement in hot-carrier lifetime as compared to aconventional surface LDD NMOS struc- ture; both n- and n= implants are aligned to the same poly gate edge. Since a longer n= region results lower substrate currents, a thermal anneal is necessary. Unfortunately, this can result in excessive lateral source/drain and gate overlap. In this disclosure, the use of a disposable frame (as described in Disclosure No. XXX Parrillo, Pfiester, and Henis) is proposed to offset then- and n= implants, thus providing a robust surface-graded LDD structure with minimum lateral n= source/drain overlap with the gate electrode The deeper arsenic or phosphorus n+ region which is aligned to the sidewall spacer edge provides low sheet and contact resistance; the shallow arsenic n- region which is aligned to disposable frame edge provides limited lateral diffusion with low series resistance; and the ultra-shallow n= phosphorus region which is aligned to the unoxidized gate edge provides lateral source/drain grading to reduce the lateral electric field and thus lower peak substrate currents. Although not shown, the corresponding structure can be realized for an LDD PMOS device using the appropriate dopant types (boron or gallium) for the p+, p-, and p= regions.