Browse Prior Art Database

PHASE LOCK LOOP

IP.com Disclosure Number: IPCOM000005769D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2001-Nov-05
Document File: 4 page(s) / 170K

Publishing Venue

Motorola

Related People

Authors:
Michael Gallup Ken Scheuer Ashok Someshwar

Abstract

The 68040 microprocessor utilizes a phase lock loop (PLL) in the generation of the microprocessor clocks. The PLL block controls the skew between the external system bus clock BCLK and the internal t368040 clock. The 68040 uses a quadrature set of clocks called "t" clocks. This skew control is performed with all digital cir- cuitry. The PLL block is comprised of seven logical blocks, a phase detector, clock control for the delay line and shifter, delay line, a linear up/down shifter, a clocking mode multiplexor, at clock generator, and a set/reset latch. Referring to Figure 1 the components of the PLL block are indicated. The PLL block uses two inputs from the external world, they are, the system bus clock BCLK and the processor clock PCLK. The PLL circuit uses three inputs from internal sources, the reset signal rsfpll, the test by-pass signal qbypass, and the test lock signal aflockx. The frequency relationship between the BCLK and the PCLK signals must always be a factor of two; the frequency of PCLK must be twice that of BCLK. Forthe current design goals, the frequency of PCLK is50MHz.