Browse Prior Art Database

METHOD FOR INSTALLING RANDOMLY SPACED INTERCONNECT PINS

IP.com Disclosure Number: IPCOM000005836D
Original Publication Date: 1990-Mar-01
Included in the Prior Art Database: 2001-Nov-09

Publishing Venue

Motorola

Related People

Authors:
Christoper R. Long

Abstract

With the continuing drive toward miniaturization of electronic products, the challenge of interconnecting parallel boards increases since it is difficult to allow enough dedicated board space for any of the commercially available ganged or strip connectors. These commercial products come with standardized patterns, typically on .lOO inch centers. Often the interconnect must occur close to the circuit origination point to minimize circuit resistance and RF spray. The ganged interconnect systems also tend to consume PCB space required to send runners to one central location where the gang- ed connector resides. The use of Interconnect Pins eliminates the space consuming header while still providing dimen- sional accuracy and interconnect pattern integrity. Additionally, the new design allows the interconnect pins to be placed "at random" such that they can be located on the board closer to their circuit's point of origin and not be confined to commercially determined spacing pattern.