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Defensive Publication for Wire bondable Tape Die Attach Disclosure Number: IPCOM000005966D
Original Publication Date: 2001-Nov-20
Included in the Prior Art Database: 2001-Nov-20

Publishing Venue


Related People

Mark Gerber Trent Thompson Shawn O'Connor


The interest in multi-chip assemblies has increased in the semiconductor industry due to competition in multiple markets. Stacked chip assemblies has emerged as one possible solution that reduces component area without increasing wafer cost (i.e. embedding memory or other functionality on chip). In stacked chip assemblies, there are a number of issues that need to be addressed to assure the final solution remains cost competitive in comparison to the individual packaged component option. These issues include low cost substrate design, assuring RF components isolation, and low cost design for test. In addition to multi-die chip assemblies, standard substrate based, high i/o, package design are also Pushing the limits of the substrate manufacturers in order reduce the necessary board space required for device placement. This has led to a number of options, including newer and more advanced substrate technologies such as HDI, but has a number of drawbacks that significantly affect the overall package cost. This paper discusses advantages of using a wire bondable die attach tape between one or multiple semiconductor chips as a low cost solution. The primary basis is that it is more expensive if a design must increase the number of layers from 2 to 4 as opposed to providing an independent power or ground layer in a separate plane (within the die attach region). The original driver for this concept was related to multi-chip packaging when considering stacking multiple die with one of them being an RF device. This is a needed for cellular phone suppliers who want to package the base-band and RF chips for a total phone solution. In addition, this solution was advantageous by allowing fewer wire bonds to the substrate thus reducing complex routing, improving manufacturibility and lower overall package cost. In further investigating this solution, integrated circuit designers found two other possible advantages of the solutions -separating the digital and analog cross talk noise and reducing potential ESD sensitivity issues within the package. These advantages in addition to possible RF shielding effects are currently being investigated.