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A Unified and Flexible Priority Scheme for Controlling a Write Buffer

IP.com Disclosure Number: IPCOM000005969D
Original Publication Date: 2001-Nov-20
Included in the Prior Art Database: 2001-Nov-20

Publishing Venue

Motorola

Related People

Authors:
Afzal Malik Bill Moyer

Abstract

Next generation portable devices are placing stringent requirements on overall system power and performance. Voice recognition, streaming video and high speed wireless internet access are just some of the features being incorporated in these handheld electronic gadgets. Therefore, some processors have been designed for high performance and cost sensitive portable products as well as for high end embedded control applications. For example, one such processor integrates a unified 16KB cache, and additional instruction pipelining and buffering to increase the operating frequency. An 8-entry write buffer which can defer pending write misses and writethrough accesses is used in order to maximize performance. In this paper, we discuss the flexible priority scheme for controlling the write buffer. We use a hardware technique which provides a flexible mechanism to control emptying and flushing of write buffer based on a set of configurable thresholds, as well as a mechanism to alter the priorities from the write buffer to the main memory system. The same unified mechanism is used to support flushing as well as providing a solution for the read after write (RAW) hazard avoidance.