ADDRESS DEPENDENT BIT ERROR CORRECTION
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2001-Nov-22
This invention relates to a POCSAG address bit error wrrection method for use in a pager. The invention provides for each address to have a unique number of allowable bit errors. Since it is possible to determine which of the ad- dresses are likely to false on a particular customer's implementation of POCSAG, falsing addresses can be programmed to 0 or 1 bit errors, thereby reducing the probability of falsely decoding the address while also reducing the sensitivity of the address. Addresses not likely to false can use the normal address correction (2 bits) and maintain normal sen- sitivity. This invention may have application to other paging protocols such as ERMES, Golay, etc.