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HIGH RESOLUTION OVERSAMPLING BIT SYNC ALGORITHM (LOW PAGER OVERSAMPLING BIT SYNC ALGORITHM)

IP.com Disclosure Number: IPCOM000006026D
Original Publication Date: 1990-Oct-01
Included in the Prior Art Database: 2001-Nov-27

Publishing Venue

Motorola

Related People

Authors:
Warren Glotzbach Zaffer Merchant Doug Ayerst

Abstract

Oversampling bit sync algorithms typically have a resolution that is equal to or less than the oversampling clock period. This means that if the oversampling clock were eight times the bit time then the algorithm would find the center of the bit to within one eighth of a bit or worse (114, 112). By employing a method that finds an edge of a bit on one phase of the oversampling clock and the center of a bit on the other phase of the oversampling clock a resolution of twice the oversampling clock can be realized. This means that if an oversampling clock of eight times the bit time is used then the algorithm will find the center of the bit to within one sixteenth of a bit or twice the resolution of the over- sampling clock. For a given required resolution, lower power can be achieved because the clock rate can be reduced by half and the desired resolution can still be achieved.