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AN ALIGNMENT-TOLERANT CONTACT PROCESS USING LANDING PADS

IP.com Disclosure Number: IPCOM000006046D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2001-Nov-28

Publishing Venue

Motorola

Related People

Authors:
Yee-Chaung See Rick Sivan

Abstract

As VLSI process technology advances, registration requirements become more stringent. These requirements are particularly important in applications with a large chip size such as microprocessors, megabit density memories where competitive cell size is critical, and high density gate arrays. One can achieve better registration through either improved registration capability using more advanced optical aligners or through innovative process techniques. The former approach is not only expensive but also more difficult because the improvement in registration capability of new equipment has not progressed at the same rate as the scaling of sub-micron feature sizes.