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Browse Prior Art Database

BOROPHOSPHOSILICATE GLASS INTERLEVEL DIELECTRIC PLANARIZATION

IP.com Disclosure Number: IPCOM000006077D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2001-Nov-30
Document File: 6 page(s) / 277K

Publishing Venue

Motorola

Related People

Authors:
F. J. Robinson

Abstract

Planarization of interlevel dielectrics is required for process flows which utilize anisotropic etching of the various layers of conductors. The vertical step formed by the anisotropic etch of an underlying layer and conformal coating of that layer with dielectric, can cause shorting bars in a subsequent conductor layer, if it is also etched anisotropically. This is because the thickness of the conductor at the steps is thicker, by the thickness of the vertical step in the underlying layer, than that on the horizontal surfaces and will take longer to etch. Figure-l demonstrates the increased thickness over steps and post-etch shorting bars.