CMOS COMBINATION INCREMENTOR WITH UNIT DELAY PER BIT
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2001-Dec-03
The incrementor implemented in the diagram below has the advantage of speed in propagating the carry from least significant bit to most significant bit. As the carry propagates, each incrementor bit cell presents only one gate delay in the carry chain. Therefore, this carry chain timing is not dependent on an RC time constant that is a limiting factor in some long word lengths. Typical delays of OSNS per incrementor stage, plus an additional 1NS delay for the last stage from 'COUT' valid to the signal 'OUT' being valid gives the following delays: 32 - BIT INCREMENTOR 17NS 16 - BIT INCREMENT'OR 9NS 8 - BIT INCREMENTOR 5NS As the name of INC-EVEN and INC-ODD indicate, the data word is built by alternating the placement of these cells for the corresponding bit position of the data word. Note that the INC-EVEN cell will increment the signal 'IN' when the CIN port is high and that the INC-ODD cell will increment the 'IN' signal when the CIN port is low. The polarity of the carry signal 'COUT' thus alternates, depending on the bit position in the data word.