Browse Prior Art Database

A DUAL PASS SCAN MECHANISM FOR MINIMIZING SERIAL SCAN OUTPUTS

IP.com Disclosure Number: IPCOM000006165D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-10
Document File: 2 page(s) / 105K

Publishing Venue

Motorola

Related People

Authors:
Eytan Hartung Mike Gladden Oded Yishay

Abstract

Testability of microprocessors and peripherals which use structured designs such as PLAs and ROMs typically require controllability and observability of these types of designs. This criteria is especially needed in microprocessors where internal access is limited. This can be accomplished through a serial shifter path or so-called "scan path" to minimize the impact on silicon area. This testing methodology typically requires a master/slave type shifter bit or so called scan latch for every input for controllability and one for every output for observability. The procedure to access a given structure is described below.