REPAIRABLE MULTI-CHIP MODULES
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-11
In today's consnmer electronic industry, reducing product size is a key initiative. A significant and ever increasing portion of the useable volume is needed for integrated circuits (ICs) and their protective packages. One commonly understood method of reducing the overall space needed for chip carriers is combining two or more KS onto a single substrate. For instance, a 80 I/O IC utilizing the latest in pad array solder attach technology takes about 0.60" of board surface.