A POWER-CONSERVING ARCHITECTURE FOR ECL BIAS VOLTAGE REGULATION
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-12
Within a BiCMOS gate array containing mostly CMOS logic with a small amount of ECL logic, the static power consumed by the ECL bias regulator net- work will be wasted if the maximum possible number of ECL gates is much larger than the number actually utilized. By reducing the "excess capacity" of the bias network, the wasted power can be eliminated.
A POWER-CONSERVING ARCHITECTURE
FOR ECL BIAS VOLTAGE REGULATION
by Michael Wang
cell itself rather than oi the base array (Figure 2). Each slave can be tailored to the requirements of the specific I/O, and thus can~ibe powered down relative to the traditional slave circuit. With a single slave in each I/O, there is no kmger any excess power con- sumed in "excess slave capacity". In addition, it is now required that the maiter regulator also be config- urable depending on the slave loading that it sees in order to maintain stability.
INTRODUCTION Extending this conceit further, the entire bias reg- ulator is placed within each macrocell that requires it
In a mixed CMOS-ECL ASK, a traditional Mas- (Figure 3). This eliminatds all unneeded bias regulator ter/Slave ECL bias generation scheme will necessitate capacity as well as simplifies the master design, since the powering up of the entire biasing network, regard- all masters now'see the pding of their single slave less of the actual amount of ECL used. A worst case and will not require re-tuning for different ldads. It scenario could be a bias regulator network capable of may also be possible to rkdesign such a bias regulator supplying several hundred ECL I/O's and some inter- so that it no longer falls
nal ECL logic but only being used for a single ECL nents and is capable o
input (Figure 1). voltages in a single sta
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