A POWER-CONSERVING ARCHITECTURE FOR ECL BIAS VOLTAGE REGULATION
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-12
Within a BiCMOS gate array containing mostly CMOS logic with a small amount of ECL logic, the static power consumed by the ECL bias regulator net- work will be wasted if the maximum possible number of ECL gates is much larger than the number actually utilized. By reducing the "excess capacity" of the bias network, the wasted power can be eliminated.