Browse Prior Art Database

PLASMA ETCH INTEGRATED CIRCUIT HOLDER

IP.com Disclosure Number: IPCOM000006190D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-12

Publishing Venue

Motorola

Related People

Authors:
Frank Bell Kelly Broeker Steven Czapski Pat Slovacek

Abstract

Internal geometries of packaged integrated circuits are frequently microprobed in order to debug new designs, improve yields, and analyze customer returns. Microprobing requires removal of the passivation and interlevel dielectric layers while maintaining device functionality. Because device geometries have shrunk and become more complex, wet processing techniques are no longer adequate. Plasma etching has improved our ability to keep the devices functional for internal probing, but the success rate has not been 100% due to the following problems: -non-uniform etching of multiple samples -chamber impedance differences between etch runs -electrostatic discharge -package heating -redeposition of metals from the package and ase electrode In order to solve these problems, a generic inte- grated circuit holder was developed for plasma etch systems. The holder consists of an aluminium block, a layer of conductive foil, an insulting plate, and heat/chemical resistive tape. These components are integrated to form a unique device which addresses all of the problems associated with plasma etching of : Slovacek its. Figures 1 and 2 illustrate ing breakdown describes the lonent addresses.