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COMBINATION OF ALIGNMENTS AND REGISTRATION TARGETS

IP.com Disclosure Number: IPCOM000006199D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-13

Publishing Venue

Motorola

Related People

Authors:
Whit G. Waldo

Abstract

Overlay of integrated circuits refers to the spatial relationship of two levels in the stack that makes a cir- cuit functional. Generally, overlay is referenced by the current level being imaged, and then either etched or implanted, to a critical previous level. Device engi- neers determine which previous level is critical to attain functionality of the circuit. Overlay involves the coupling of critical dimension control of features on the two levels and the registration of the two levels. The paradigm in integrated circuit fabrication pro- cesses is to use an alignment target design recom- mended by the manufacturer to align the mask to the wafer and to use a separate registration structure to measure the success in alignment.