SPLIT REDUNDANT IMPLEMENTATION OF DUAL CLOCK DEVICES
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-13
An IC (e.g. ASK, microprocessor, etc.) that has a primary oscillator input, a secondary oscillator input, and a clock output (Figure l), can be combined with one or more similar devices to reduce the number of oscillator circuits needed for fail-safe operation by uti- lizing the clock output signals of the complementary device(s).