CMOS REDUCED DELAY TEST MULTIPLEXER
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-14
When testing circuits, a test multiplexer is often node IN high. When a ,logical 0 is required to be required on the inputs and outputs of logic blocks. A passed by the test multiplexer, transistor Nl is turned logic block may consist of an entire chip, such as on and node IN is driven low. Actually, IN is not when JTAG is used, or may be a section of a chip. driven to a true electrical 0: it is only driven low The new design removes a significant portion of the enough so that the next stage of logic interprets its delay introduced by conventional multiplexers. voltage as a logical 0. Since CMOS has inherently Instead of adding additional logic to the signal path, large noise margins, IN does not need to be driven the new design is attached to the signal path so that it much lower than the threshold voltage. Figure 2 can overdrive the signal that would otherwise propa- shows how a p-channel transistor could be used as part gate to the logic block under test. As a result, the only of the new multiplexer. Note that here it is assumed delay penalty is due to additional drain capacitance, that the circuit input can be held at a logical 1 during which is much less than the delay of addition logic in test mode operation. It can be easily shown that Nl the signal path. During test, the new design will dissi- (Pl) only needs to be able to sink (source) slightly pate static current. However, during normal operation, more current that INV can source (sink) for the next the design is disabled and there is no static current. stage of logic to function correctly.