A NEW DESIGN APPROACH TO IMPROVE ACQUISITION TIME OF PHASE-LOCKED LOOP (pll) SYSTEMS
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-14
Abstract-This disclosure describes a new design approach being used in order to improve the pll acquisition (lock-in) time. A new circuit is added in order to initialize the loop filter node at a voltage level close to the center between VDD and VSS so that the lock-in (acquisition) time of the phase-locked loop system will have an improvement (reduction) of at least 10 times over present state of the art of HCMOS technology. The loop filter is a part of a high fre- quency phase locked loop system which is used as a part of a high performance data communication chip.