A SINGLE-POLY C-BiCMOS PROCESS WITH ADVANCED ITLDD CMOS AND SELF-ALIGNED VERTICAL NPN, PNP DEVICES
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-17
BiCMOS process has received much attention for high-speed applications. However, scaling of the con- ventional BiCMOS processes and devices to sub-pm has raised some issues. Reduction of supply voltage is necessary for conventional sub-pm MOSFETs due to 'reliability concerns (especially HCI). This reduction causes delay and reduced output voltage in the BiC- MOS gates due to the fixed Vbe drops in NPN. To minimize the impact of voltage reduction, CBiCMOS processes having vertical PNP devices may be used. These processes usually are very complicated and high cost.