Browse Prior Art Database

IMPROVED DATA TRANSFER SYNCHRONIZATION MECHANISM

IP.com Disclosure Number: IPCOM000006241D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-18
Document File: 3 page(s) / 129K

Publishing Venue

Motorola

Related People

Authors:
Mark G. Spiotta

Abstract

When transferring data between two asynchronous devices via an intermediate mailbox register, some fortn of synchronization mechanism is required to pre- vent the mailbox from being updated at the same time that it is being read. The most prevalent hardware synchronization mechanism is double-buffering, which allows the first buffer to be updated while the second buffer is simultaneously accessed. This tech- nique works well and is efficient when a small number of mailboxes are involved. However, because a dou- ble-buffered mailbox requires over twice the amount of circuitry as an unprotected mailbox, the cost of double buffering can be prohibitive when a large array of mailboxes needs to be protected.