Browse Prior Art Database

IMPROVED GExSI1-x w MOSFET WITH Ge MONOLAYER INSERTION

IP.com Disclosure Number: IPCOM000006243D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-18
Document File: 3 page(s) / 156K

Publishing Venue

Motorola

Related People

Authors:
X. Theodore Zhu Herb Goronkin

Abstract

There is currently considerable interest in MOS- gated Ge,Si,., heterostructures [l-4] to improve pMOS device performance. By burying a layer of narrow gap Ge,Si,., under the gate of a pMOS transistor, one creates a potential well in the valence band to confine holes in the high-performance Ge,Si,., layer. Unfortunately, the valence band-edge offset AE, at the Ge,Si,JSi interface is not large enough to adequately confine the holes. For example, for the case of com- monly used Ge fraction of x=0.2 the offset is a mere AE,=O.l5eV.