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DUAL CLOCK FLIP FLOP Resolving Skew Between Commonly Generated Clocks Disclosure Number: IPCOM000006244D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-18

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Richard A. Erhart


Skew problems between clocks continues to be a source of design problems in modem circuit design. Circuits which must communicate with each other but use clock sources emanating from different locations or sources have to resolve the skew problems between these clocks to communicate properly. This can be an intensive simulation problem in both board level or IC level design. The parasitics due to the physical layout must be estimated for proper simulation. This paper discusses a new design for a Flip Flop that will resolve these problems without intensive simulation by the designer. The cost is minimal because the Flip Flop can be designed as a custom element and then used in a "Cell Design" approach.