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IP.com Disclosure Number: IPCOM000006245D
Original Publication Date: 1991-Jul-01
Included in the Prior Art Database: 2001-Dec-18

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Gerald A. Keller


Manufacturing timetables to meet customer demands for integrated circuits can push the process engineer into production with little time for lengthy qualifi,cation procedures. Some equipment, such as SEM and optical critical dimension measuring equip- ment that provide valuable data to the engineer require significant time delays to gather necessary informa- tion. Availability of the critical dimension measuring equipment for develop module setup is also an issue. Because of this, and the need to make adjustments to the equipment in a timely manner anyway, the method described here has found application. In this method a light, uniform exposure dose is applied across the pho- toresist coated wafer substrate and then developed. By observing pattern colorations in the developed film, adjustments to the hardware, etc. are made to optimise develop and process uniformity across the wafer substrate. During the initial setup phase of a photolithographic process, contrast (the slope found by taking the linear regression of the normalized resist thickness versus the logarithm of the exposure dose at a fixed develop process time) and Eo (threshold or the exposure dose at which the photoresist film develops out) are determined (Figure 1).